1. Field of the Invention
This disclosure relates generally to a semiconductor device and, more particularly, to a field effect transistor (FET) device having a fin-shaped channel and a method of fabricating the FET device.
2. Description of the Related Art
Along with advances in semiconductor technology, a semiconductor integrated circuit (IC) device becomes faster in operation and higher integrated. To continue performance enhancement of the device and reduction in leakage current, device design engineers have researched and developed a variety of new device structures available for sub-10 nm generations. One promising device structure is a field effect transistor device having a fin-shaped channel (finFET), such as the structure recently proposed by Chenming Hu et al. of the Regents of the University of California, USA.
This finFET device structure features a transistor channel that is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin, and two gates that are self-aligned to each other and to the source/drain regions. Thus, this structure may also be referred to as a self-aligned double-gate finFET.
FIG. 1 is a plan diagram illustrating a conventional finFET device. FIG. 2 is a cross-sectional diagram further illustrating the conventional finFET device, and taken along the line II-II in FIG. 1.
Referring to FIGS. 1 and 2, the finFET device is fabricated on a silicon substrate 8 that is covered with an insulating layer 7. A vertically extended channel fin 3 is provided on the substrate 8 and is covered with a gate oxide layer 5. Raised source/drain regions 1 and 2 are provided at both ends of the channel fin 3 on the substrate 8. The source/drain regions 1 and 2 are connected by the channel fin 3. A gate 6 is disposed between the source/drain regions 1 and 2 and extends across the channel fin 3. Additionally, a gate spacer (not shown) may be formed on both sides of the gate 6.
Unfortunately, the conventional finFET device described above may also have some drawbacks. For example, the conventional finFET device may need complicated fabricating processes since, if a number of channels are formed, a corresponding number of source/drain regions are required. Complicated processes may increase the likelihood of errors. Furthermore, the shrinkage of pattern dimensions may require increased doping impurity concentrations. This may result in an increase of leakage current, and thereby device characteristics, such as refresh time, are degraded.
Embodiments of the invention address these and other disadvantages of the conventional art.